RISC-V 32-bit IM (RV32IM) CPU - More details will be added in the future

This project delivers a 45 nm FreePDK45 5-stage pipelined RV32IM RISC-V CPU integrating OpenRAM SRAM macro for L1 cache, synthesized to standard cells and physically implemented in Cadence Innovus to a timing-verified, routed layout.

Layout
Figure 1: Layout.
Clock Tree
Figure 2: Clock Tree.
CPU Layout (memory excluded)
Figure 3: CPU Layout (memory excluded).
Full layout amoeba view
Figure 4: Full layout amoeba view.
uncompleted trial
Figure 5: Some other uncompleted trial.

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