The Multiply-Accumulate (MAC) module is a pipelined digital circuit designed to compute the accumulation of products between a 4-bit signed input and a 4-bit signed weight over multiple clock cycles. Specifically, it processes one multiplication per cycle, accumulates the result over 8 cycles, and outputs a 12-bit signed result on the 9th cycle.
The design incorporates internal registers for input synchronization, multiplication, and accumulation stages, ensuring correct timing and data stability under a 1 GHz clock. The MAC module was verified through testbenches with a variety of input patterns and synthesized with standard cell libraries, satisfying timing constraints and maintaining functional equivalence across RTL and gate-level simulations.