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Experience and Leadership

Experience 1 Image

Spintronics Research in Physical Electronics Research Laboratory

Developed a high-speed true random number generator using MTJs, validated with NIST tests. Designed full-stack PCB hardware, characterized MTJs, and built custom C++ tooling for integration.

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Experience 2 Image

Undergraduate Teaching Assistant in CE 203 - Introduction to Computer Engineering

Provided hands-on support to 80+ students in digital logic and LC-3 assembly. Led 36 office hours and graded lab assignments while assisting with lab instrumentation and conceptual understanding.

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Experience 3 Image

Treasurer - IEEE Northwestern Student Branch

Managed a $5,000 budget to fund 10+ tech events, workshops, and guest talks. Supported 50+ members and led all finance operations for the chapter.

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Relevant Projects

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Non-Volatile Logic-in-Memory FPGA Design with MTJs

Designed and implemented a digital circuit layout using 45nm technology in a custom CAD flow.

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Project 2 Image

CAD Engine for VLSI Applications with Magnetic and RF Components

Built a Python tool with GUI and simulated annealing to optimize VLSI floorplans with RF/magnetic constraints.

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Project 4 Image

Real-Time Magnetic Field Scanner

Designed a joystick-controlled AMR scanner with Hall trigger; visualized 3D fields in Python. 3rd place at MMM-Intermag 2025.

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Project 5 Image

Embedded Systems - Flappy Bird Game on nRF52833

Developed a voice-controlled Flappy Bird game on nRF52833 with RTOS, touchscreen, and MEMS mic integration.

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Project 7 Image

Braille-Grid - IEEE Northwestern Chapter Project Competition 2024

Implemented the Hardware of Grid Actuators for Visually-Impaired Users

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Project 8 Image

Automatic Signaling Jacket

Developed a wearable signaling system using motion sensors for cyclists. Automatically triggers turn signals based on body lean, built in C++ and demonstrated at national competitions.

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Relevant Class Assignments

Project 6 Image

Multiplication-Accumulation Module in Verilog (CE 303)

Implemented a pipelined 4-bit signed MAC for ASIC flow; verified with XCelium and synthesized to 28nm.

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Project 3 Image

4x4 SRAM Design (CE 391)

Designed a 4x4-bit SRAM in 45nm CMOS; verified functionality and achieved 500 MHz operation.

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Education

Master of Science in Electrical Engineering

Northwestern University • 2026-2027

Bachelor of Science in Computer Engineering

Northwestern University • 2023-2026

Relevant Courses

Contact

Email: [email protected] Copied!